DenseMem CXL memory expansion
DenseMem increases effective CXL Type 3 Device memory capacity by a factor of 2x through transparent, in-line memory compression/decompression with minimal impact to latency and badwidth. DenseMem is available as an area and power efficient drag and drop IP block portable across the latest process nodes.
Overview
DenseMem increases effective CXL Type 3 Device memory capacity by a factor of 2-3x through transparent, in-line memory compression/decompression with minimal impact to latency and badwidth. DenseMem is available as an area and power efficient drag and drop IP block portable across the latest process nodes.
Standards
Protocol: CXL 2.0, 3.0, 3.1, cxl.mem
Compression: LZ4, ZSD (proprietary)
AMBA interface: AXI4, CHI
Architecture
Transparent addressing to host over CXL.mem
Arbitrary cache line read/ write
Bridge to cxl.mem, optionally to cxl.io
Compliant to the OCP-specified interface “Hyperscale CXL Tiered Memory Expander Specification”
Partial support for DCD
Type 3 device support, Memory tiering
Features
Turn key solution: compression, decompression, compaction, memory management, remapping
Automatic compressed memory tier
Multi-instance support to match interface throughput
Cache line granularity decompression for highest read performance (proprietary algorithm)
Deliverables
FPGA evaluation license
Encrypted IP delivery (Xilinx)
HDL source Licenses
Synthesizable System Verilog RTL (encrypted)
Implementation constraints
UVM testbench (self-checking)
Vectors for testbench and expected results
User Documentation
Applications
Data Center operators at scale regularly employ software memory compression to create an additional memory tier to conserve capacity and interconnect bandwidth. Such operations consume monetizable host node compute cycles. DenseMem offloads compression/ decompression , tranparently creating a new, dynamically adjusting compressed memory tier within the Type 3 Device. DenseMem free up host cycles to service end user workloads. DenseMem supports industry standard compression algorithms for compatibility/ interoperability and alternatively offers propreitary compression algorithms for highest performance. DenseMem AI features adapt performance by adjusting to workloads automatically.
Integration
DenseMem can be integrated into the CXL Type 3 device SoC, between the CXL controller and memory controller logic blocks, supporting both AXI4 and CHI specifications. DenseMem lightweight firmware enables communication with the device over CXL.mem commands when reading and writing pages. DenseMem exposes compressed memory region as an additional Tier in the memory hierarchy, for easy integration into existing linux and software application stacks as well as CXL fabric management software.
Benefits
2-3x effective capacity increase. New compressed memory tier instantiated automatically inside CXL Type 3 device. Turn key solution: Real-time compression/decompression coupled with compaction, and transparent memory management. Operations at main memory speed and throughput. Compatible with AXI4/CHI specifications for easy integration. Intelligent real-time analysis and tuning to adapt to diverse workloads.
Performance / KPI
| Feature | Performance |
| Compression ratio: | 2-3x across diverse data sets |
| Frequency: | 1.6GHz (@5nm TSMC) |
| IP area: | Starting at 0.23mm2 (@5nm TSMC) 75% is SRAM |
| Memory technologies supported: | (LP)DDR4, (LP)DDR5 |
System integration of DenseMem
Integrated within a CXL Type 3 device
Cache MX
The Cache MX compression solution increases the cache capacity by 2x at an 80% area and power saving to comparable SRAM capacity.
Ziptilion™ MX
High performance and low latency hardware accelerated compression at unmatched power efficiency.
Ziptilion™ BW
Delivers up to 25% more (LP)DDR bandwidth at nominal frequency and power, enabling a significantly more performance and energy efficient SoC.
DenseMem
Double the CXL connected memory capacity with data DenseMem.
NVMe expansion
Extend NvMe storage capacity 2-4x with LZ4 or zstd hardware accelerated compression.
SphinX
High Performance and Low Latency AES-XTS industry-standard encryption / decryption. Independent non-blocking encryption and decryption channels.