ZeroStorage
A high-performance hardware accelerator for LZ4-compatible compression and decompression, built for clean integration into ASIC and FPGA designs targeting storage and SSD controllers.
What it does
ZeroStorage accelerates standards-based LZ4 compression and decompression in hardware. It is fully software compatible and transparent to the host file system, so it drops into existing storage stacks without changing data formats.
At a glance
LZ4-compatible, fully software compatible
Asymmetric compressor / decompressor
ASIC and FPGA targets (Intel, AMD)
AMBA AXI4-Stream interface
Transparent to the host file system
Where it fits
Storage and media: accelerate compression and decompression for storage and SSD controllers.
DRAM memory: improve bandwidth utilization and capacity through real-time compression.
Streaming data: efficient compression for high-throughput streaming workloads.
Asymmetric by design
The compressor and decompressor can be configured and instantiated completely independently, so you only spend area on the direction and performance you actually need.
Why customers select it
Maximum flexibility through extensive configuration options.
Industry-leading performance per mm² for LZ4 acceleration.
Efficient silicon footprint for advanced ASIC processes and leading Intel and AMD FPGA platforms.
We chose ZeroPoint because we have confidence in their expertise and support, and they are delivering according to schedule at the quality that meets our standards.
Chinese hyperscaler
Key specifications
Default configuration benchmarks (8KB block, Samsung 4nm / TSMC N5). Silicon area figures are configuration dependent.
| Standard | LZ4-compatible compression and decompression. |
| Target implementation | ASIC or FPGA, for SoC integration. |
| Operating frequency | 1.6 GHz target (compressor and decompressor). |
| Compressor throughput | 1.89 GB/s average, 2.98 GB/s peak (8KB block). |
| Decompressor throughput | 5.05 GB/s average, 11.48 GB/s peak (8KB block). |
| Compression ratio | 1.88x average on the Silesia dataset (software LZ4 reference: 2.1x). |
| Interfaces | AMBA AXI4-Stream data interface, single clock domain. Exposed custom SRAM memory interface. |
| Configuration options | Block size, frame vs block format compatibility, large block support via system DRAM, and broad design space exploration. |
LZ4 software compatibility
| Feature | Support |
| Compression levels 1–12 | Supported |
| Block sizes 64KB, 256KB, 1MB, 4MB | Supported |
| Block independence and block dependency | Supported |
| Frame content size | Supported |
| Block mode, streaming mode, frame integrity checks | Full support |
| Sparse mode, favor-decompression-speed | Not supported |
What's included
Encrypted RTL with a top-level reference design, for compressor and decompressor.
Clean-text testbench and a complete UVM verification framework.
Integration and user guide documentation.
Standard LZ4 public C-models.
FPGA flow support for Intel (Quartus) and AMD (Vivado).
ASIC flow support for Cadence and Synopsys.
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