What do you do when the SRAM scaling stops? Read the Cache expansion whitepaper!

Moore’s Law has been the key to performance scaling of computers. For decades, the number of transistors per die doubled with each new technology generation (a.k.a. technology node) every two years. Processor architects could successfully translate this transistor doubling to a doubling of compute performance.

Up until ca 2002, a primary means for compute performance doubling was to increase the clock frequency exponentially with each new technology node while keeping the power budget under control. After 2002, however, frequency scaling halted as it was not possible anymore to keep power in cheque and architectural changes was the only alternative left. This opened the era of multicore scaling in which the number of processors (a.k.a. cores) per die doubles with each new technology node. By doubling the number of cores, one can get twice as much work done per time unit, thereby doubling compute performance with each new technology node. However, twice as many cores needs twice as much on-chip cache. Hence, the amount of cache memory on a die has essentially doubled with each new technology node.

Up until very recently multicore scaling has worked well due to the healthiness of Moore’s Law. Unfortunately, it has been clear for some time that it gets increasingly harder to enjoy the same rate of transistor scaling for SRAM cells as for logic. At the 68th IEEE International Electron Devices Meeting in December 2022, TSMC disclosed that their 3nm technology node offered practically no improvement in SRAM density over its previous 5 nm node. Lacking SRAM scaling, this leads to only a 50% increase in performance per technology node rather than 100% using multicore scaling. While work is underway in search of new memory technologies that can replace SRAM (e.g., STT-RAM) these technologies are far from mature for deployment. With ZeroPoint Technology, one can use a proprietary ultrafast lossless compression technology to enjoy continued SRAM scaling. Read all about it in this whitepaper.